cryogenic current steering dac with mitigated variability
| Description | |
| Date | 2020 |
| Date | |
| Auteurs | Zurita,- M | Le guevel,- L | Billiot,- G | Morel,- A | Jehl,- X | Jansen,- A | Pillonnet,- G | |
| Source | IEEE Solid-State Circuits Letters | |
| Résumé | The paper presents an 8-bit differential current steering digital-to-analog converter (DAC) for the cryogenic front-end of future quantum computers. Recently published characterization of CMOS technology reveals the deterioration of transistor matching properties at cryogenic temperatures. The preliminary study of current mismatch in the FDSOI technology at 4.2 K allows proper sizing of the 255 current-source unit cells to mitigate non-linearities and optimize the static DAC performance. Based on this study we minimize the power consumption while maintaining the targeted non-linearity,- i.e. 7.3 |W for DNL=0.64 LSB. With a 6.6 mV output range and 26 B5V voltage step,- our DAC is compatible with the foreseen requirements for fine-grain biasing a Si-based qubit matrix at an expected 100MS/s on-chip output drive. IEEE |
| DOI | http://dx.doi.org/10.1109/LSSC.2020.3013443 |
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